Publications

Some highlighted publications from researchers affiliated with the center can be found below.

Surveys

Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides, “Deep Neural Network Approximation for Custom Hardware: Where We’ve Been, Where We’re Going”, ACM CSUR 2019, https://arxiv.org/abs/1901.06955

Stylianos I. Venieris, Alexandros Kouris, Christos-Savvas Bouganis, “Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions”, ACM CSUR 2018, https://arxiv.org/abs/1803.05900

Arithmetic for Deep Learning

Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides, “LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference”, https://arxiv.org/abs/1910.12625. Includes open-source software at https://github.com/awai54st/LUTNet

George A. Constantinides, “Rethinking Arithmetic for Deep Neural Networks”, https://arxiv.org/abs/1905.02438

Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides, “LUTNet: Rethinking Inference in FPGA Soft Logic”, in Proc. FCCM 2019, https://arxiv.org/abs/1904.00938

Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert Mullins, Peter Cheung, George Constantinides and Chengzhong Xu, “Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs”, in Proc. FPT 2019.

Architecture for Deep Learning

A. Boutros, S. Yazdanshenas, and V. Betz, “Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs,” FPL 2018, pp. 1 – 8, http://www.aboutros.info/fpl2018.pdf

A. Boutros, M. Eldafrawy, S. Yazdanshenas and V. Betz, “Math Doesn’t Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs,” FPGA 2019, pp. 94 – 193, http://www.aboutros.info/fpga2019.pdf

SeyedRamin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, and Philip H.W. Leong. LUXOR: an FPGA logic cell architecture for efficient compressor tree implementations. FPGA 2020. https://arxiv.org/abs/2003.03043

Mapping Deep Neural Networks to Hardware

C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong, “Optimizing FPGA-based accelerator design for deep convolutional neural networks,” In Proc. FPGA, 2015. https://doi.org/10.1145/2684746.2689060

Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Leong, Magnus Jahre, and Kees Vissers. FINN: a framework for fast, scalable binarized neural network inference. In Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 65–74. 2017. https://arxiv.org/abs/1612.07119

Julian Faraone, Nicholas Fraser, Michaela Blott, and Philip H.W. Leong. SYQ: learning symmetric quantization for efficient deep neural networks. In Proc. Computer Vision and Pattern Recognition (CVPR). June 2018. https://arxiv.org/abs/1807.00301

Stylianos I. Venieris, Christos-Savvas Bouganis, “Mapping Regular and Irregular Convolutional Neural Networks on FPGAs”, IEEE Transactions on Neural Networks and Learning Systems, 30(2), Feb 2019. https://doi.org/10.1109/TNNLS.2018.2844093

Ruizhe Zhao and Wayne Luk, “Efficient Structured Pruning and Architecture Searching for Group Convolution,” Proc. ICCV NEUARCH Workshop, 2019. https://arxiv.org/abs/1811.09341

M. Vasileiadis, C.-S. Bouganis, G. Stavropoulos and D. Tzovaras, “Optimising 3D-CNN Design Towards Human Pose Estimation on Low Power Devices”, Proc. BMVC 2019. https://bmvc2019.org/wp-content/uploads/papers/0327-paper.pdf

A. Kouris, S.I. Venieris, and C.-S. Bouganis, “Towards Efficient On-board Deployment of DNNs on Intelligent Autonomous Systems”, Proc. ISVLSI 2019, http://cas.ee.ic.ac.uk/people/alk15/files/ISVLSI_2019_dnn_deployment.pdf

A. Montgomerie-Corcoran, S.I. Venieris, and C.-S. Bouganis, “Power-Aware FPGA Mapping of Convolutional Neural Networks”, Proc. ICFPT 2019, https://doi.org/10.1109/ICFPT47387.2019.00059.

H. Fan, G. Wang, M. Ferianc, X. Niu, and W. Luk, “Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGA”, Proc. ICFPT 2019, https://doi.org/10.1109/ICFPT47387.2019.00012.

Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan Moss, Peter Zipf, and Philip H. W. Leong. Unrolling ternary neural networks. ACM Trans. Reconfigurable Technol. Syst., 12(4):22:1–22:23, October 2019. https://arxiv.org/abs/1909.04509

Training on Non-Traditional Architectures

Cheng Luo, Man-Kit Sit , Hongxiang Fan, Shuanglong Liu, Wayne Luk, Ce Guo, Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism, in Proc. FCCM 2019, https://doi.org/10.1109/FCCM.2019.00016

Sean Fox, Julian Faraone, David Boland, Kees Vissers, and Philip H.W. Leong. Training deep neural networks in low-precision with high accuracy using FPGAs. In Proc. International Conference on Field Programmable Technology (FPT) https://doi.org/10.1109/ICFPT47387.2019.00009

Miscellaneous

Further publications can be found at:


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