Some highlighted publications from researchers affiliated with the center can be found below.


Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides, “Deep Neural Network Approximation for Custom Hardware: Where We’ve Been, Where We’re Going”, ACM CSUR 2019,

Stylianos I. Venieris, Alexandros Kouris, Christos-Savvas Bouganis, “Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions”, ACM CSUR 2018,

Arithmetic for Deep Learning

George A. Constantinides, “Rethinking Arithmetic for Deep Neural Networks”,

Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides, “LUTNet: Rethinking Inference in FPGA Soft Logic”, in Proc. FCCM 2019,

Architecture for Deep Learning

A. Boutros, S. Yazdanshenas, and V. Betz, “Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs,” FPL 2018, pp. 1 – 8,

A. Boutros, M. Eldafrawy, S. Yazdanshenas and V. Betz, “Math Doesn’t Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs,” FPGA 2019, pp. 94 – 193,

Mapping Deep Neural Networks to Hardware

C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong, “Optimizing FPGA-based accelerator design for deep convolutional neural networks,” In Proc. FPGA, 2015.

Stylianos I. Venieris, Christos-Savvas Bouganis, “Mapping Regular and Irregular Convolutional Neural Networks on FPGAs”, IEEE Transactions on Neural Networks and Learning Systems, 30(2), Feb 2019.

Training on Non-Traditional Architectures

Cheng Luo, Man-Kit Sit , Hongxiang Fan, Shuanglong Liu, Wayne Luk, Ce Guo, Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism, in Proc. FCCM 2019,


Further publications can be found at:

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